Timing Specifications
Table 3.4 Write Cycle Timing 1 (W Controlled) 1
MR4A08B
Parameter
Write cycle time 2
Address set-up time
Address valid to end of write (G high)
Address valid to end of write (G low)
Write pulse width ( G high)
Write pulse width (G low)
Data valid to end of write
Data hold time
Write low to data Hi-Z 3
Write high to output active 3
Write recovery time
Symbol
t AVAV
t AVWL
t AVWH
t AVWH
t WLWH
t WLEH
t WLWH
t WLEH
t DVWH
t WHDX
t WLQZ
t WHQX
t WHAX
Min
35
0
18
20
15
15
10
0
0
3
12
Max
-
-
-
-
-
-
-
-
12
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
2
3
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must
remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being
asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
This parameter is sampled and not 100% tested. Transition is measured ±200 mV from the steady-state voltage. At any given
voltage or temperature, t WLQZ (max) < t WHQX (min)
Figure 3.4 Write Cycle Timing 1 (W Controlled)
t AVAV
A (ADDRESS)
E (CHIP ENABLE)
W (WRITE ENABLE)
t AVWL
t AVWH
t WLEH
t WLWH
t WHAX
t DVWH
t WHDX
D (DATA IN)
t WLQZ
DATA VALID
Q (DATA OUT)
Hi -Z
Hi -Z
t WHQX
Copyright ? Everspin Technologies 2013
9
MR4A08B Rev. 6 9/2013
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